Electrically erasable and electrically programmable read-only memories (EEPROMS) are widely used in the art of integrated circuits. Flash memories are a particular form of EEPROMS that can be quickly erased. Generally, flash EEPROM cells may be formed as stacked gates or as split gates. Referring now to FIG. 18, a prior art stack gate, a flash EEPROM device 225, is shown in simplified form. The device comprises an MOS transistor having a substrate or bulk 200, a source and drain 204, and a complex gate 208, 212, 216, and 220. The gate comprises a control gate electrode 220 and a floating gate electrode 212. The floating gate electrode 212 is a conductive film that is separated from the substrate 200 by a tunnel oxide 208 and that is separated from the control gate electrode 220 by an inter-gate dielectric 216.
The memory device 225 is essentially an MOSFET having a variable threshold voltage (Vth). As in any MOSFET, the charge carrier conductivity of the channel region 206 between the source and drain regions 204 is controlled by a voltage on the gate 220, 216, 212, and 208. In the flash device case, voltages are applied to the control gate electrode 220 while the floating gate electrode 212 is isolated. If the control gate electrode 220 voltage exceeds the Vth of the device 225, then current will be conducted from drain 204 to source 204 under a drain to source bias. If the Vth exceeds the control gate electrode 220 bias, then the drain to source current will be shut OFF. In this way, the relative Vth of the flash device can be read. In a memory scheme, the variable Vth is programmed to represent a memory state, such as ‘0’ or ‘1’.
A quantity of charge can be stored on the floating gate electrode 212. It is the presence of this charge that alters the Vth of the device 225. For example, if a p-type substrate 200 is used, then the memory device 225 would be an NMOS type flash device 225 is formed. To conduct current from drain to source 204, the p-type substrate 200 must be inverted at the substrate channel 206. Note that the stack of control gate 220 and floating gate 212 overlying the channel region 206 creates a capacitor divider. Therefore, any voltage applied to the control gate electrode 220 is divided according to the coupling ratios between the control and floating gates and between the floating gate and substrate. A sufficiently large positive voltage bias on the control gate 220 will cause an accumulation of negative carriers (electrons) at the substrate 200 surface in the channel region 206 as is typical in an NMOS device. If a negative charge is stored on the floating gate electrode 212, then the value of the positive voltage on the control gate electrode 220 necessary to invert the channel must be increased to compensate.
The device 225 is erased by biasing the control gate electrode 220, drain 204, source 204, and substrate 200 such that electrons are injected from the drain 204, source 204, or substrate 200 through the tunnel oxide layer 208 and onto the floating gate electrode 212. This negative charge on the floating gate electrode 212 will raise the Vth of the device 225 by several volts. The device 225 is programmed by biasing the control gate electrode 220, drain 204, source 204, and substrate 200 such that electrons are removed from the floating gate electrode 212 through the tunnel oxide layer 208 and into the substrate 200.
To ensure a complete erasing of all the cells in the erasing block during the erasing process, the erasing bias conditions are normally sustained for a prolonged period of time. There are occasions when this prolonged erasing operation results in the removal of excessive electrons from the floating gate electrode 212 such that the floating gate is positively charged. In a memory device 225 that has been severely over-erased, the floating gate 212 charge condition causes the device to operate as a depletion device. That is, the memory device 225 conducts drain-to-source current even when the control gate electrode 220 has a zero bias or is floating. This is called over erasure.
To overcome over erasure, split gate flash memory devices have been constructed in the art. In a split gate device, the stacked gate, comprising a control gate overlying a floating gate, is present over only a part of the channel region of the device between source and drain. In another part of the channel region, the control gate electrode overlies the substrate without an intervening floating gate. In this way, the floating gate can be used to alter the Vth of the device, yet, the control gate can turn OFF the channel even if the floating gate is over-erased.